An interline CCD imaging array with on-chip A/D conversion

In this paper we describe an interline CCD imaging array which features high-speed, on-chip, parallel A/D conversion. In addition, we present test results from fabricated devices. The imaging chip was fabricated through MOSIS in a double-poly 2:0m CCD/CMOS technology on a chip with total area 2:25mm 2:22mm. The chip is composed of two components, namely, a 28 39 pixel, interline imaging array and a bank of 39, single-slope CCD/CMOS A/D converters; the converters function in parallel to achieve eeective high-speed A/D conversion. Chip output is a stream of 8-bit digital data in which each 8-bit value corresponds to the light level at a pixel. Once an image has been captured, a set of parallel CCD shift registers transfer the data one column at a time to the parallel A/D converters. The analog data from each column is then converted in parallel and the resulting digital values are read out serially. In each row, the area cost of the A/D conversion circuitry is approximately the area occupied by eight pixels. This cost scales with the number of rows and the number of bits desired for the digital output and not with the number of columns. Ultimately, counter and control circuitry used to drive the single slope conversion can all be implemented on-chip, resulting in a single chip imager with direct digital output.